1. Field of the Invention
The present invention relates to a semiconductor device wherein a vertical type power MOSFET and a Schottky barrier diode are integrated on a common semiconductor chip and a method of manufacturing the same.
2. Description of the Prior Art
As shown in FIG. 1A, a vertical type power MOSFET device is so formed that a plurality of P.sup.+ type base regions 2 are formed on a surface of an N.sup.- type layer 1 of an N.sup.+ /N.sup.- substrate, an N.sup.+ type source region 3 is formed on a surface of the base regions 2, a gate electrode 4 is formed over a channel region in the base regions 2, and a source electrode 5 is formed to make ohmic contact with both the base regions 2 and the source region 3. Such power MOSFET device has excellent features such as simple circuit configuration in contrast to a bipolar device, so that it has been employed particularly as a switching device (for instance, see Patent Application Publication (KOKAI) 7-15009).
As one of applications of the power MOSFET device, a switching device used in a DC--DC converter, for example, can be considered. As shown in FIG. 1B, in the switching device used in the DC--DC converter, a collector of a PNP transistor 7 and a drain of an N channel MOSFET device 8 are connected commonly, and the PNP transistor 7 and the N.sup.- channel MOSFET device 8 are alternately turned ON/OFF. Where a reference 9 denotes a parasitic diode which is formed parasitically by PN junction between the P.sup.+ 0 type base region 2 and the N.sup.- type layer 1.
In the circuit wherein alternate ON/OFF operations would be repeated, a so-called reverse recovery time becomes an issue when the N.sup.- channel MOSFET device 8 is transferred from an OFF state to an ON state since current flows from a coil (not shown) connected to a current path via a capacitor (not shown) and the parasitic diode 9 in the N.sup.- channel MOSFET device 8, for example, when the PNP transistor 7 is in an OFF state.
This reverse recovery time is defined as a time required for discharging completely carriers (electrons) accumulated in the N.sup.- type layer 1 via the parasitic diode 9 to recover the PN junction of the parasitic diode 9. Thus, the N.sup.- channel MOSFET device 8 cannot turn ON during the reverse recovery time even if an ON signal is applied to a gate of the N.sup.- channel MOSFET device 8. As a result, an all over switching time of the circuit cannot be improved due to such reverse recovery time.
For this reason, as shown in FIG. 1C, a Schottky barrier diode (SBD) 10 is connected parallel to the parasitic diode 9. By falling down the drain potential of the N.sup.- channel MOSFET device 8 quickly to the source potential based on the fact that a forward voltage VF of the SBD 10 is lower than the PN diode 9, it is intended to improve the all over switching time of the circuit.
However, if the above circuit is constituted by discrete devices, the number of parts is increased to thus disturb miniaturization of the electronic devices. Hence, although the case has been considered where the FET chip and the SBD chip are mounted in one package, several problems have arisen. By way of example, these chips would be wasted if the number of good quality parts of the FET chip disagrees with that of the SBD chip since these chips are manufactured by employing independent wafers, and also assembling process of these chips would become complicated.
In the event that the FET and the SBD are formed by discrete devices to overcome the above problems, there is caused a problem that, since the FET and the SBD are mounted on the substrate and then conductive patterns or connecting the FET to the SBD are formed on the substrate, the conductive patterns acts as noise generating sources to badly influence their peripheral circuits.